1. Field of the Invention
This invention relates generally to the apparatus and process used in plasma-based etching. More specifically, this invention teaches an apparatus and a process to perform plasma etching by using a double wafer parallel plate RF plasma etching system.
2. Description of the Prior Art
Parallel plate plasma etching used in integrate circuit (IC) manufacture is limited by several difficulties including the problems of stray electrical discharges, the low etching efficiency, and the asymmetry and nonuniformity in plasma currents during etching. Since the ability to develop and build ever so smaller microelectronic devices depends strongly on the capability to generate a desired device pattern in an image layer by lithography and then transfer this pattern into the layers of materials by etching process, improvement to plasma etching performance is critically important. Parallel plate plasma etching system which is commonly used in dry etching process offers higher accuracy in replicating device patterns than the wet etching processes.
A parallel plate plasma etching system generally has a reactor chamber containing a pair of electrodes to which RF power is applied. A wafer including a film thereon to be etched is then placed on one of the electrodes. The electrode whereon the wafer is placed is commonly referred to as a chuck electrode whereas the opposite electrode without a wafer is termed as a counter electrode. Suitable gases are injected into the chamber and plasma is formed to etch the film. High or low radio frequencies are used in the etching process dependent upon the type of film being etched. Such a system is called a single wafer parallel plate plasma etching system.
In order to enhance the etch rate, it is desirable to induce a high voltage across the electrodes, imparting high energy levels to the system. One undesirable consequence of applying high voltage across the electrodes is the resulting excessive stray electrical discharges from the electrodes to the reactor chamber wall and other parts in the system. In order to circumvent this problem, several designs are proposed to minimize the potential difference between either electrode and the reactor chamber wall while maintaining a high voltage difference between the two electrodes.
U.S. Pat. No. 4,626,312 to Tracy entitled "Plasma Etching System for Minimizing Stray Electrical Discharges" Dec. 2, 1986), proposes that stray electrical discharges may be reduced by dividing the applied voltage between the chuck and counter electrodes while maintaining the etching chamber at a ground potential. Because of the asymmetries in the construction of the reactor vessel, electrodes, and electrical feed lines, as well as the unbalanced impedance load placed on the counter electrode by the wafer, a precise division of the voltage can not be fully effected and the theoretical maximum voltage can not be realized.
U.S. Pat. No. 4,871,421 to Ogle and Yin entitled "Split Phase Driver for Plasma Etch System" (Oct. 3, 1989) utilizes an elaborated split-phase driver to deal with the problem of intrinsic electrical asymmetry of single wafer system in order to achieve a precise 180 degree phase difference and therefore the maximum voltage difference between the two electrodes.
Even that a single wafer etching system as proposed by Ogle et al. is able to generate a greater electrode voltage difference, it is still limited by the unresolved problems of low etching efficiency and the asymmetrical etching performance which is inherent in its wafer placement on a single electrode. Additionally, during the half cycle of the RF voltage when the chuck electrode having a voltage higher than that at counter electrode, current flows from chuck electrode to counter electrode. Energetic ions bombard the counter electrode instead of the wafer disposed on chuck electrode. Consequently, not only that power is wasted, damage of counter electrode occurs while the electrode is bombarded by ions without the shielding of a wafer.